Advanced design techniques of CMOS amplifiers oriented to robust settling-time optimization
Tutor: Prof. Gianluca Giustolisi
The activity aims to the development of a new design procedure for the robust design of amplifiers for being certain that an OTA satisfies the settling-time constraint under any statistical variation of process or design parameters.
Study cycle:
post graduate
Languages skills required:
English B1
Length:
2 months
Period:
second semester
Summer traineeships:
no
Research centre/company involved:
Lab: Microelectronic Design Laboratory http://www.dieei.unict.it/it/corsi/lm-29/aule-e-laboratori
Insurance:
Accident insurance during working hours only and Liability insurance
Benefits:
none
Traineeship type:
non Erasmus placement
A.Y.:
2019-2020